1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device, and a method for producing a semiconductor device.
2. Background Information
Recently, significant attention has been given to SOI (Silicon on Insulator)-MOS technology as one technique to achieve higher integration, higher performance, and lower power consumption in semiconductor devices. The following description describes a conventional method for producing an SOI-MOS transistor.
First, an SOI substrate composed of a silicon support substrate, a buried oxide (BOX) film, and a silicon semiconductor layer (SOI layer) is employed, and a field oxide film is formed by a LOCOS (Local Oxidation of Silicon) process or the like, thus, elements are separated. Then, a gate insulating film is formed on the silicon semiconductor layer, and a polysilicon film is additionally formed on the gate insulating film. After a gate electrode is formed by lithography or etching, a low concentration of impurity ions is introduced, thus, an extension region is formed.
Next, a silicon oxide film is deposited by a CVD (Chemical Vapor Deposition) process, and etch back is performed on the silicon oxide film by anisotropic etching. Thus, a sidewall portion is formed. In this etch back process, over etching is performed on the surface of the silicon semiconductor layer in a drain region and a source region of a MOS transistor. Thus, the thicknesses of the regions become thinner than the initial thicknesses thereof.
Subsequently, a silicon epitaxial layer is formed by selective epitaxial growth (SEG) performed on the silicon semiconductor layer in the drain region and the source region. Besides, in selective epitaxial growth, since a crystal also grows on the polysilicon film, a silicon crystal grows also on the upper part of the gate electrode where the surface of polysilicon is exposed.
After the above process is conducted, the MOS transistor is formed through processes such as implantation of a high concentration of impurity ions into the drain and source regions, and the formation of electrode by using silicide.
A semiconductor device including a MOS transistor produced by a semiconductor process is disclosed in Japanese Laid-Open Patent Publication TOKUKAI No. 2001-68666 (especially pages 3–4, FIGS. 1–2), though the semiconductor device does not have an SOI substrate, for example.
The semiconductor device disclosed in JP 2001-68666 has a double sidewall structure composed of a first sidewall portion with an L-shape when viewed in a cross-section of oxide film and a second sidewall portion extending from the side surfaces to a bottom surface of the first sidewall portion of the nitride film. Although the semiconductor device has an electric-field-relaxing structure formed by using LDD (Lightly Doped Drain), implantation of low concentration impurity ions into the extension region is performed after formation of the gate electrode, in other words, previous to the formation of the first and second sidewall portions. Since this semiconductor device does not employ an SOI substrate but a conventional bulk substrate, the silicon semiconductor layer in the drain and source regions has sufficient thickness, thus, the parasitic resistance is small. Accordingly, thickness adjustment for the silicon semiconductor layer by using selective epitaxial growth is not necessary.
Typically, in an SOI substrate, a silicon semiconductor layer (SOI layer) is thin having a thickness of the order of several tens nm. When a silicide electrode is directly formed on a silicon semiconductor layer, the silicide electrode cannot be formed with a sufficient thickness. This causes an increase in sheet resistance. Accordingly, with an SOI-MOS transistor, a technique, which increases the thickness of silicon to the thickness necessary for formation of a silicide electrode with low resistance by growing silicon in drain and source regions by selective epitaxial growth (elevated source/drain structure), is used.
However, in the case that selective epitaxial growth is performed on a thin silicon semiconductor layer, silicon aggregates in the case of growth at typical growth temperatures (for example, 800° C.). The amount of aggregation is inversely proportional to the thickness of the silicon. That is, such aggregation becomes more remarkable as a silicon semiconductor layer is thinner. As mentioned above, in the conventional method for producing an SOI-MOS transistor, over etching is performed on the surface of the silicon semiconductor layer in the etch back process in the formation of the sidewall portion. As a result, the silicon semiconductor layer becomes thinner, and thus, silicon tends to aggregate. Accordingly, it is difficult to provide a silicon epitaxial film with the desired film quality.
Furthermore, implantation of a low concentration of impurity ions into the extension region, so-called extension ion implantation, is performed in order to reduce the resistance value of the silicon semiconductor layer corresponding to the region directly under the sidewall portion. Since the silicon semiconductor layer is thin throughout, this causes large parasitic resistance and reduces the drive power of a MOS transistor.
With the semiconductor device disclosed in JP 2001-68666, the double sidewall structure is composed of the first sidewall portion with an L-shape and the second sidewall portion extending from the side surfaces to the bottom surface of the first sidewall portion, as mentioned above. According to the downscaling of the semiconductor device, reduction of the resistance value directly under the sidewall portion becomes an important issue, particularly with SOI-MOS transistors, whose importance has been indicated. When a double sidewall structure similar to this semiconductor device is applied to a SOI-MOS transistor, the thickness of a double sidewall in the SOI-MOS is almost the same as that of a thick single sidewall that is applied to the SOI-MOS. The reason is that the first sidewall has a L-shape, and even if the side portion of the first sidewall is thinly formed, the bottom portion of the first sidewall needs to have a given length. In an SOI substrate, a semiconductor layer (SOI layer) is thin having a thickness on the order of several tens nm. Accordingly, if the width of the sidewall portion were large, the parasitic resistance directly under the sidewall portion would become large. With the semiconductor device disclosed in the JP 2001-68666 employing a bulk substrate, the device has a semiconductor layer directly under the sidewall portion with a sufficient thickness. Hence, reduction of parasitic resistance by thickness adjustment of the semiconductor layer in the drain and source regions is not taken into consideration.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and method for producing the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.